SH7263 Datasheet, PDF (185/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Bit
Bit Name
7
IRQ7F
6
IRQ6F
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
[Legend]
n = 7 to 0
Initial
Value
0
0
0
0
0
0
0
0
R/W Description
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ Interrupt Request
These bits indicate the status of the IRQ7 to IRQ0
interrupt requests.
Level detection:
0: IRQn interrupt request has not occurred
[Clearing condition]
R/(W)*
R/(W)*
R/(W)*
• IRQn input is high
1: IRQn interrupt has occurred
[Setting condition]
• IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
• Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
• Cleared by executing IRQn interrupt exception
handling
1: IRQn interrupt request is detected
[Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
Rev. 2.00 Mar. 14, 2008 Page 151 of 1824
REJ09B0290-0200