SH7263 Datasheet, PDF (1221/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
(7) Data Transfer FIFO and Data Register
• The 224-byte data FIFO register (FLDTFIFO) is incorporated for data transfer of flash
memory.
• The 32-byte control code FIFO register (FLECFIFO) is incorporated for data transfer of
control code.
(8) DMA Transfer
• By individually specifying the destinations of data and control code of flash memory to the
DMA controller, data and control code can be sent to different areas.
(9) Access Time
• The operating clock (FCLK) on the pins for the AND-/NAND-type flash memory is generated
by dividing the peripheral clock (Pφ).
• The division ratio can be specified by the FCKSEL bit and the QTSEL bit in the common
control register (FLCMNCR).
• Before changing the CPG specification, the FLCTL must be placed in a module stop state.
• In NAND-type flash memory, the FSC and FWE pins operate with the FCLK frequency. In
AND-type flash memory, the FSC pin operates with the FCLK operating frequency and the
FWE pin operates with a frequency half the FCLK operating frequency. The operating
frequencies must be specified within the maximum operating frequency of memory to be
connected.
Rev. 2.00 Mar. 14, 2008 Page 1187 of 1824
REJ09B0290-0200