SH7263 Datasheet, PDF (1004/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit 10 to 8 — Cycle Count Maximum (CMAX): Indicates the maximum number of CCR. The
number of basic cycles available in the matrix cycle for Timer Triggered transmission is (Cycle
Count Maximum + 1).
Unless CMAX = 3'b111, RCAN-TL1 is in time-trigger mode and time trigger function is
available. If CMAX = 3'b111, RCAN-TL1 is in event-trigger mode.
Bit[10:8]: CMAX[2:0]
000
001
010
011
100
101
110
111
Description
Cycle Count Maximum = 0
Cycle Count Maximum = 1
Cycle Count Maximum = 3
Cycle Count Maximum = 7
Cycle Count Maximum = 15
Cycle Count Maximum = 31
Cycle Count Maximum = 63
CCR is cleared and RCAN-TL1 is in event-trigger mode. (initial value)
Important: Please set CMAX = 3'b111 when event-trigger mode is used.
Bits 7 to 4: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 3 to 0 — Tx-Enable Window (TEW): Indicates the width of Tx-Enable Window. TEW =
H'00 shows the width is one nominal Bit Timing. All values from 0 to 15 are allowed to be set.
Bit[3:0]: TEW[3:0]
Description
0000
The width of Tx-Enable Window = 1 (initial value)
0001
The width of Tx-Enable Window = 2
0010
The width of Tx-Enable Window = 3
0011
The width of Tx-Enable Window = 4
....
......
....
......
1111
The width of Tx-Enable Window = 16
Note: The CAN core always needs a time between 1 to 2 bit timing to initiate transmission. The
above values are not considering this accuracy.
Rev. 2.00 Mar. 14, 2008 Page 970 of 1824
REJ09B0290-0200