SH7263 Datasheet, PDF (134/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
USB_X2
USB_X1
CKIO
On-chip oscillator
Divider 1
×1
× 1/2
× 1/4
PLL circuit 1
(× 8,12,16)
Crystal
oscillator
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
× 1/12
Crystal
oscillator
MD_CLK1
MD_CLK0
CPG control unit
Clock frequency
control circuit
Standby control circuit
FRQCR
Bus interface
MTU clock
(Iφ, Max. 200 MHz)
Peripheral clock
(Pφ, Max. 33.33 MHz)
Bus clock
(Bφ = CKIO, Max. 66.66 MHz)
[Legend]
FRQCR: Frequency control register
Peripheral bus
Figure 4.1 Block Diagram of Clock Pulse Generator
Rev. 2.00 Mar. 14, 2008 Page 100 of 1824
REJ09B0290-0200