SH7263 Datasheet, PDF (445/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the source of the DMA transfer request from peripheral modules in each channel.
DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4
and 5, and DMARS3 is for channels 6 and 7. Table 10.4 shows the specifiable combinations.
DMARS can specify the following transfer request sources: eight SCIF sources, eight IIC3
sources, one A/D converter source, five MTU2 sources, and two CMT sources, two USB sources,
two FLCTL sources, four SSI sources, two SRC sources, four SSU sources, one ROM-DEC
source, two SDHI sources.
Two RCAN-TL sources do not need to be specified by these registers, for these two sources can
be specified using the RS3 to RS0 bits in the DMA channel control register (CHCR).
• DMARS0
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH1 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH1 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH0 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH0 RID[1:0]
0
0
R/W R/W
• DMARS1
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH3 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH3 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH2 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH2 RID[1:0]
0
0
R/W R/W
• DMARS2
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH5 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH5 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH4 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH4 RID[1:0]
0
0
R/W R/W
• DMARS3
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH7 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH7 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH6 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH6 RID[1:0]
0
0
R/W R/W
Rev. 2.00 Mar. 14, 2008 Page 411 of 1824
REJ09B0290-0200