SH7263 Datasheet, PDF (19/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

15.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 720
15.3.5 Serial Mode Register (SCSMR)............................................................................ 721
15.3.6 Serial Control Register (SCSCR).......................................................................... 724
15.3.7 Serial Status Register (SCFSR) ............................................................................ 728
15.3.8 Bit Rate Register (SCBRR) .................................................................................. 736
15.3.9 FIFO Control Register (SCFCR) .......................................................................... 746
15.3.10 FIFO Data Count Set Register (SCFDR) .............................................................. 749
15.3.11 Serial Port Register (SCSPTR) ............................................................................. 750
15.3.12 Line Status Register (SCLSR) .............................................................................. 753
15.3.13 Serial Extension Mode Register (SCEMR)........................................................... 754
15.4 Operation ........................................................................................................................... 755
15.4.1 Overview............................................................................................................... 755
15.4.2 Operation in Asynchronous Mode ........................................................................ 758
15.4.3 Operation in Clock Synchronous Mode................................................................ 769
15.5 SCIF Interrupts .................................................................................................................. 777
15.6 Usage Notes ....................................................................................................................... 778
15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 778
15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 778
15.6.3 Restriction on DMAC Usage ................................................................................ 779
15.6.4 Break Detection and Processing ........................................................................... 779
15.6.5 Sending a Break Signal......................................................................................... 779
15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 779
15.6.7 Selection of Base Clock in Asynchronous Mode.................................................. 781
Section 16 Synchronous Serial Communication Unit (SSU) ............................783
16.1 Features.............................................................................................................................. 783
16.2 Input/Output Pins ............................................................................................................... 785
16.3 Register Descriptions ......................................................................................................... 786
16.3.1 SS Control Register H (SSCRH) .......................................................................... 787
16.3.2 SS Control Register L (SSCRL) ........................................................................... 789
16.3.3 SS Mode Register (SSMR) ................................................................................... 790
16.3.4 SS Enable Register (SSER) .................................................................................. 791
16.3.5 SS Status Register (SSSR) .................................................................................... 793
16.3.6 SS Control Register 2 (SSCR2) ............................................................................ 796
16.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 797
16.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 798
16.3.9 SS Shift Register (SSTRSR)................................................................................. 799
16.4 Operation ........................................................................................................................... 800
16.4.1 Transfer Clock ...................................................................................................... 800
16.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 800
Rev. 2.00 Mar. 14, 2008 Page xix of xxxiv
REJ09B0290-0200