SH7263 Datasheet, PDF (1376/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.21 Packet Reception and Buffer Memory Clearing Processing
Register Setting
DCLRM = 0
Buffer Status
When Packet is Received
BFRE = 0
BFRE = 1
Buffer full
Doesn't need Doesn't need
to be cleared to be cleared
Zero-length packet reception
Needs to be Needs to be
cleared
cleared
Normal short packet reception
Doesn't need Needs to be
to be cleared cleared
Transaction count ended
Doesn't need Needs to be
to be cleared cleared
DCLRM = 1
BFRE = 0
Doesn't need
to be cleared
Doesn't need
to be cleared
Doesn't need
to be cleared
Doesn't need
to be cleared
BFRE = 1
Doesn't need
to be cleared
Doesn't need
to be cleared
Doesn't need
to be cleared
Doesn't need
to be cleared
(e) BRDY Interrupt Timing Selection Function
By setting the BFRE bit setting in PIPECFG, it is possible to keep the BRDY interrupt from being
generated when a data packet consisting of the maximum packet size is received.
When using DMA transfers, this function can be used to generate an interrupt only when the last
data item has been received. The last data item refers to the reception of a short packet, or the
ending of the transaction counter. When the BFRE bit is set to 1, the BRDY interrupt is generated
after the received data has been read. When the DTLN bit in DnFIFOCTR is read, the length of
the data received in the last data packet to have been received can be confirmed.
Table 25.22 shows the timing at which the BRDY interrupts are generated by this module.
Rev. 2.00 Mar. 14, 2008 Page 1342 of 1824
REJ09B0290-0200