SH7263 Datasheet, PDF (233/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
1, 0
SZ[1:0]
00
R/W Operand Size Select
Select the operand size of the bus cycle for the break
condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
7.3.6 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle
is set before or after instruction execution.
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
3. Specifies whether a trigger signal is output to the UBCTRG pin when a break condition is
satisfied.
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
- UTOD1 UTOD0 CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCMFC SCMFC SCMFD SCMFD
0
1
0
1
-
-
-
-
- PCB1 PCB0 -
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R R R/W R/W R R R R R
Bit
Bit Name
31 to 20 ⎯
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 199 of 1824
REJ09B0290-0200