SH7263 Datasheet, PDF (1158/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)
The CD-ROM decoder reset control register (ROMDECRST) resets the random logic of the CD-
ROM decoder and clears the RAM in the CD-ROM decoder.
Bit:
Initial value:
R/W:
7
LOGI
CRST
0
R/W
6
RAM
RST
0
R/W
5
-
0
R/W
4
-
0
R/W
3
-
0
R/W
2
-
0
R/W
1
-
0
R/W
0
-
0
R/W
Bit Bit Name
Initial
Value R/W Description
7
LOGICRST 0
R/W CD-ROM Decoder Random Logic Reset Signal
A reset signal is output while this bit is set to 1.
6
RAMRST
0
R/W CD-ROM Decoder RAM Clearing Signal
Refer to the RAMCLRST bit in the RSTSTAT register to
confirm that RAM clearing is complete.
5 to 0 ⎯
All 0 R/W Reserved
These bits are always read as 0.The write value should
always be 0.
Note: Before setting LOGICRST to 1, make sure that the RAMRST bit is cleared to 0 and then
write B'10000000 to this register.
Rev. 2.00 Mar. 14, 2008 Page 1124 of 1824
REJ09B0290-0200