SH7263 Datasheet, PDF (142/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
2. The frequency of the peripheral clock is as follows:
In mode 0
In mode 1
the frequency on the EXTAL pin × the frequency-multiplier of the PLL
circuit × the divisor of the divider 1
(the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
In mode 3 (the frequency on the USB_X1 pin × 1/4) × the frequency-multiplier of
the PLL circuit × the divisor of the divider 1
The frequency of the peripheral clock should be set to 33.33 MHz or less, and should
not be set higher than the frequency on the CKIO pin.
3. The frequency multiplier of PLL circuit can be selected as ×8, × 12 or × 16. The
divisor of the divider can be selected as × 1, × 1/2, × 1/3, × 1/4, × 1/6, × 1/8, or ×
1/12. The settings are made in the frequency-control register (FRQCR).
4. The output frequency of the PLL circuit is as follows:
In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL
circuit
In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of
the PLL circuit
In mode 2/3 (the frequency on the CKIO pin or the USB_X1 pin × 1/4) ×
the frequency-multiplier of the PLL circuit
Ensure that the output frequency of the PLL circuit should be 200 MHz or less.
Rev. 2.00 Mar. 14, 2008 Page 108 of 1824
REJ09B0290-0200