SH7263 Datasheet, PDF (1079/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.3.14 IEBus Lock Address Register 2 (IELA2)
IELA2 specifies the upper four bits of a locked address when a unit is locked.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
ILAU4
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 4
3 to 0
Initial
Bit Name Value R/W
⎯
All 0 R
ILAU4
0000 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Upper Four Bits of IEBus Locked Address
Stores the upper four bits of the master unit address
when a unit is locked. These bits are valid only when
the LCK bit in IEFLG is set
Rev. 2.00 Mar. 14, 2008 Page 1045 of 1824
REJ09B0290-0200