SH7263 Datasheet, PDF (1395/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
(2) Transfer Schedule
This section describes the transfer scheduling within a frame of this module. After the module
sends an SOF, the transfer is carried out in the sequence described below.
1. Execution of periodic transfers
A pipe is searched in the order of Pipe 1 → Pipe 2 → Pipe 6 → Pipe 7, and then, if the pipe is
one for which an isochronous or interrupt transfer transaction can be generated, the transaction
is generated.
2. Setup transactions for control transfers
The DCP is checked, and if a setup transaction is possible, it is sent.
3. Execution of bulk and control transfer data stages and status stages
A pipe is searched in the order of DCP → Pipe 1 → Pipe 2 → Pipe 3 → Pipe 4 → Pipe 5, and
then, if the pipe is one for which a bulk or control transfer data stage or a control transfer status
stage transaction can be generated, the transaction is generated.
If a transfer is generated, processing moves to the next pipe transaction regardless of whether
the response from the peripheral is ACK or NAK. Also, if there is time for the transfer to be
done within the frame, step 3 is repeated.
(3) USB Communication Enabled
Setting the UACT bit of the DVSTCTR register to 1 initiates sending of an SOF or μSOF, and
makes it possible to generate a transaction.
Setting the UACT bit to 0 stops the sending of the SOF or μSOF and initiates a suspend state. If
the setting of the UACT bit is changed from 1 to 0, processing stops after the next SOF or μSOF is
sent.
Rev. 2.00 Mar. 14, 2008 Page 1361 of 1824
REJ09B0290-0200