SH7263 Datasheet, PDF (1830/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
16.6.2 Note on
823
Continuous
Transmission/Reception
in SSU Slave Mode
17.3.2 I²C Bus Control 833
Register 2 (ICCR2)
18.1 Features
867
18.5.2 Note on Using ⎯
Oversampling Clock
19.2 Architecture
908
Figure 19.1 RCAN-TL1
architecture
Revision (See Manual for Details)
Newly added
Table amended
Initial
Bit
Bit Name Value R/W Description
1
IICRST
0
R/W IIC Control Part Reset
Resets bits BC2 to BC0 in the ICMR register and the
IIC3 internal circuits. If this bit is set to 1 when hang-up
occurs because of communication failure during I²C bus
operation, bits BC2 to BC0 in the ICMR register and the
IIC3 internal circuits can be reset by setting this bit to 1.
Description amended and note added
• Selects the oversampling clock input from among the
following pins:
EXTAL, XTAL (Clock operation modes 0 and 1: 10 MHz to
33.33 MHz)
CKIO (Clock operation mode 2: 40 MHz to 50 MHz*)
AUDIO_CLK (1 MHz to 40 MHz)
AUDIO_X1, AUDIO_X2
(crystal resonator connected: 10 MHz to 40 MHz;
external clock input: 1 MHz to 40 MHz)
Note: * Do not select CKIO as the source for the
oversampling clock when using a CKIO frequency
exceeding 50 MHz in clock operation mode 2.
Deleted
Legend and note added
[Legend]
n = 0, 1
Note:
The core of the RCAN-TL1 is designed with a 32-bit
bus system as the basis, but the RCAN-TL1 overall
uses a 16-bit bus interface for communication with the
CPU, including the MPI. Longword (32-bit) accesses
are converted into two consecutive word accesses by
the bus interface.
Rev. 2.00 Mar. 14, 2008 Page 1796 of 1824
REJ09B0290-0200