SH7263 Datasheet, PDF (783/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
15.3.10 FIFO Data Count Set Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
T[4:0]
-
-
-
R[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 13 —
12 to 8 T[4:0]
7 to 5 —
4 to 0 R[4:0]
Initial
Value
All 0
00000
All 0
00000
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R T4 to T0 bits indicate the quantity of non-transmitted
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
R Reserved
These bits are always read as 0. The write value should
always be 0.
R R4 to R0 bits indicate the quantity of receive data
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
Rev. 2.00 Mar. 14, 2008 Page 749 of 1824
REJ09B0290-0200