SH7263 Datasheet, PDF (1626/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 33 User Debugging Interface (H-UDI)
33.2 Input/Output Pins
Table 33.1 Pin Configuration
Pin Name
Symbol I/O
Function
Clock pin for H-UDI serial data TCK
I/O
Input
Data is serially supplied to the H-UDI from
the data input pin (TDI), and output from
the data output pin (TDO), in
synchronization with this clock.
Mode select input pin
H-UDI reset input pin
TMS
TRST
Input
Input
The state of the TAP control circuit is
determined by changing this signal in
synchronization with TCK. For the protocol,
see figure 33.2.
Input is accepted asynchronously with
respect to TCK, and when low, the H-UDI is
reset. TRST must be low for a constant
period when power is turned on regardless
of using the H-UDI function. See section
33.4.2, Reset Configuration, for more
information.
H-UDI serial data input pin TDI
Input
Data transfer to the H-UDI is executed by
changing this signal in synchronization with
TCK.
H-UDI serial data output pin
ASE mode select pin
TDO
Output
ASEMD* Input
Data read from the H-UDI is executed by
reading this pin in synchronization with
TCK. The initial value of the data output
timing is the TCK falling edge. This can be
changed to the TCK rising edge by
inputting the TDO change timing switch
command to SDIR. See section 33.4.3,
TDO Output Timing, for more information.
If a low level is input at the ASEMD pin
while the RES pin is asserted, ASE mode is
entered; if a high level is input, product chip
mode is entered. In ASE mode, dedicated
emulator function can be used. The input
level at the ASEMD pin should be held for
at least one cycle after RES negation.
Note: * When the emulator is not in use, fix this pin to the high level.
Rev. 2.00 Mar. 14, 2008 Page 1592 of 1824
REJ09B0290-0200