SH7263 Datasheet, PDF (1290/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
13
SBUSY
0
R/W SIE Buffer Busy
0: SIE is not being accessed.
1: SIE is being accessed.
12 to 0 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: Only reading 0 and writing 1 are valid.
25.3.10 Transaction Counter Registers (D0FIFOTRN, D1FIFOTRN)
D0FIFOTRN and D1FIFOTRN are registers that are used to set the number of DMA transfer
transactions and read the number of transactions.
These registers are initialized by a power-on reset and a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRNCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name
TRNCNT
[15:0]
Initial
Value
H'0000
R/W Description
R/W Transaction Counter
These bits are valid when data is being read from the
buffer memory.
The number of transactions that is being counted can
be read when the TRENB bit in DnFIFOSEL is set to
1. If the TRENB bit is cleared to 0, the set number of
transactions can be read.
W: Sets the number of DMA transfer transactions
R: Reads the number of transactions
Rev. 2.00 Mar. 14, 2008 Page 1256 of 1824
REJ09B0290-0200