SH7263 Datasheet, PDF (1093/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.3.19 IEBus Receive Interrupt Enable Register (IEIER)
IEIER enables/disables interrupts for sources such as IERSR receive busy, receive start, receive
normal completion, and receive error completion.
Bit: 7
6
RXBYSE RXSE
Initial value: 0
0
R/W: R/W R/W
5
4
3
RXFE
RXEDEE
RXE
OVEE
0
0
0
R/W R/W R/W
2
RXE
RTMEE
0
R/W
1
0
RXE
DLEE
RXEPEE
0
0
R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
RXBSYE 0
R/W Receive Busy Interrupt Enable
Enables/disables a receive busy interrupt (RXBSY)
0: Disables a receive busy (RXBSY) interrupt
1: Enables a receive busy (RXBSY) interrupt
6
RXSE
0
R/W Receive Start Interrupt Enable
Enables/disables a receive start (RXS) interrupt
0: Disables a receive start (RXS) interrupt
1: Enables a receive start (RXS) interrupt
5
RXFE
0
R/W Receive Normal Completion Enable
Enables/disables a receive normal completion (RXF)
interrupt
0: Disables a receive normal completion (RXF) interrupt
1: Enables a receive normal completion (RXF) interrupt
4
RXEDEE 0
R/W Broadcast Receive Error Interrupt Enable
Enables/disables a broadcast receive error (RXEDE)
interrupt
0: Disables a broadcast receive error (RXEDE) interrupt
1: Enables a broadcast receive error (RXEDE) interrupt
Rev. 2.00 Mar. 14, 2008 Page 1059 of 1824
REJ09B0290-0200