SH7263 Datasheet, PDF (659/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Normal Mode
Figure 11.113 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in normal mode after re-setting.
MTU2 module output
TIOC*A
1
2
3
RESET TMDR TOER
(normal) (1)
4
5
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10 11 12 13 14
Error PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.113 Error Occurrence in Normal Mode, Recovery in Normal Mode
1. After a reset, MTU2 output is low and ports are in the high-impedance state.
2. After a reset, the TMDR setting is for normal mode.
3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
4. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
5. Set MTU2 output with the PFC.
6. The count operation is started by TSTR.
7. Output goes low on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR.
11. Not necessary when restarting in normal mode.
12. Initialize the pins with TIOR.
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Rev. 2.00 Mar. 14, 2008 Page 625 of 1824
REJ09B0290-0200