SH7263 Datasheet, PDF (827/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
16.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit: 7
6
5
- ORER -
Initial value: 0
0
0
R/W: R R/W R
4
3
2
1
0
- TEND TDRE RDRF CE
0
0
1
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
⎯
0
R
6
ORER
0
R/W
5, 4 ⎯
All 0 R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either. Note
that this bit has no effect during slave data receive
operation (MSS in SSCRH cleared to 0 and TE and RE
in SSER set to 0 and 1, respectively) in SSU mode
(SSUMS in SSCRL cleared to 0).
[Setting condition]
• When one byte of the next reception is completed
with RDRF = 1 (except during slave data reception
in SSU mode)
[Clearing condition]
• When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 793 of 1824
REJ09B0290-0200