SH7263 Datasheet, PDF (829/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Initial
Bit
Bit Name Value R/W
0
CE
0
R/W
Section 16 Synchronous Serial Communication Unit (SSU)
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. In SSU mode, when
clearing RDRF in SSSR while reading receive data
(reading SSRDR) when a slave device is in the receive
operation state, or clearing TDRE in SSSR while writing
transmit data (writing to SSTDR) when a slave device is
in the transmit operation state, an incomplete error
occurs at the end of the frame, even if clearing does not
complete by the beginning of the next frame.
Data reception does not continue while the CE bit is set
to 1. Serial transmission also does not continue. Reset
the SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting conditions]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
• At the end of the frame, when reading SSRDR and
clearing RDRF do not complete by the beginning of
the next frame during receive operation by a slave
device
• At the end of the frame, when writing to SSTDR and
clearing TDRE do not complete by the beginning of
the next frame during transmit operation by a slave
device
[Clearing condition]
• When writing 0 after reading CE = 1
Rev. 2.00 Mar. 14, 2008 Page 795 of 1824
REJ09B0290-0200