SH7263 Datasheet, PDF (1143/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03)
The pre-ECC correction header: mode data register (HEAD03) indicates the mode value in the
header before ECC correction.
Bit: 7
6
5
4
3
2
1
0
HEAD03[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
HEAD03[7:0]
Initial
Value
All 0
R/W Description
R
Mode value in the header before ECC correction
21.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00)
The pre-ECC correction subheader: file number (byte 16) data register (SHEAD00) indicates the
file number value in the subheader before ECC correction (byte 16).
Bit: 7
6
5
4
3
2
1
0
SHEAD00[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit Bit Name
Initial
Value R/W Description
7 to 0 SHEAD00[7:0] All 0 R
Indicates file number value in the subheader before
ECC correction (byte 16).
For sectors not in Mode 2, this register contains the
byte of data at the corresponding position.
Rev. 2.00 Mar. 14, 2008 Page 1109 of 1824
REJ09B0290-0200