SH7263 Datasheet, PDF (1325/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.32 Pipe Configuration Register (PIPECFG)
PIPECFG is a register that specifies the transfer type, buffer memory access direction, and
endpoint numbers for PIPE1 to PIPE7. It also selects continuous or non-continuous transfer mode,
single or double buffer mode, and whether to continue or disable pipe operation at the end of
transfer.
This register is initialized by a power-on reset or a software reset. Only the TYPE1 and TYPE0
bits are initialized by a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
TYPE[1:0]
-
-
-
BFRE
DBLB CNTMD
SHT
NAK
-
Initial value: 0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R R/W R/W R/W R/W R
5
4
3
2
1
0
-
DIR
EPNUM[3:0]
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
15, 14 TYPE[1:0]
13 to 11 ⎯
Initial
Value R/W
00
R/W
All 0 R
Description
Transfer Type
• PIPE1 and PIPE2
00: Pipe use disabled
01: Bulk transfer
10: Setting prohibited
11: Isochronous transfer*
• PIPE3 to PIPE5
00: Pipe use disabled
01: Bulk transfer
10: Setting prohibited
11: Setting prohibited
• PIPE6 and PIPE7
00: Pipe use disabled
01: Setting prohibited
10: Interrupt transfer
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1291 of 1824
REJ09B0290-0200