SH7263 Datasheet, PDF (1481/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
27.3 Operation
27.3.1 Initial Setting
Figure 27.2 shows a sample flowchart for initial setting.
Start initial setting
Set necessary parameters.
Set the SRCEN bit in SRCCTRL to 1
Initial setting completed
Register
Bit
Items to be Set
SRCCTRL
EEN
Enabling/disabling of the OVF interrupt
IFS[3:0]
Input sampling rate
OFS
Output sampling rate
SRCIDCTRL IED
Input data endian
IEN
Enabling/disabling of the IDE interrupt
IFTRG[1:0] Input data FIFO triggering number
SRCODCTRL OCH
Exchanging of output data channels
OED
Output data endian
OEN
Enabling/disabling of the ODF interrupt
OFTRG[1:0] Output data FIFO triggering number
Figure 27.2 Sample Flowchart for Initial Setting
Rev. 2.00 Mar. 14, 2008 Page 1447 of 1824
REJ09B0290-0200