SH7263 Datasheet, PDF (1235/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3.6 Data Counter Register (FLDTCNTR)
FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or
written in command access mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECFLW[7:0]
DTFLW[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
DTCNT[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 24 ECFLW[7:0] All 0
23 to 16 DTFLW[7:0] All 0
15 to 12 —
All 0
11 to 0 DTCNT[11:0] All 0
R/W Description
R FLECFIFO Access Count
Specify the number of longwords in FLECFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLECFIFO.
In FLECFIFO read, these bits specify the number of
longwords of the data that can be read from FLECFIFO.
In FLECFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLECFIFO.
R FLDTFIFO Access Count
Specify the number of longwords in FLDTFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLDTFIFO.
In FLDTFIFO read, these bits specify the number of
longwords of the data that can be read from FLDTFIFO.
In FLDTFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLDTFIFO.
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Data Count Specification
Specify the number of bytes of data to be read or written
in command access mode. (Up to 2048 + 64 bytes can be
specified.)
Rev. 2.00 Mar. 14, 2008 Page 1201 of 1824
REJ09B0290-0200