SH7263 Datasheet, PDF (1827/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
16.4.5 SSU Mode
810
(3) Data Reception
Figure 16.7 Example of
Reception Operation
(SSU Mode)
Revision (See Manual for Details)
Figure amended
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
1 frame
SSCK
SSI
RDRF
Bit Bit Bit Bit Bit Bit Bit Bit
01234567
SSRDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit
76543210
SSRDR0 (MSB first transmission)
LSI operation
User operation Dummy-read SSRDR0
SSRXI interrupt
generated
Read SSRDR0
SSRXI interrupt
generated
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
01234567 01234567
SSRDR1
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
7654321076543210
SSRDR0
SSRDR1
LSI operation
User operation Dummy-read SSRDR0
SSRXI interrupt generated
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
Bit
0
to
Bit Bit
70
to
Bit Bit
70
to
Bit
7
Bit
0
to
Bit
7
SSRDR3
SSRDR2
SSRDR1
SSRDR0
Bit _to Bit Bit _to Bit Bit _to Bit Bit _to Bit
7
07
07
07
0
SSRDR0
SSRDR1
SSRDR2
SSRDR3
LSI operation
User operation Dummy-read SSRDR0
SSRXI interrupt generated
Rev. 2.00 Mar. 14, 2008 Page 1793 of 1824
REJ09B0290-0200