SH7263 Datasheet, PDF (1039/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
19.5 Interrupt Sources
Table 19.2 lists the RCAN-TL1 interrupt sources. These sources can be masked. Masking is
implemented using the mailbox interrupt mask registers (MBIMR) and interrupt mask register
(IMR). For details on the interrupt vector of each interrupt source, see section 6, Interrupt
Controller (INTC).
Table 19.2 RCAN-TL1-n*¹ Interrupt Sources
Interrupt Description
Interrupt Flag DMAC Activation
ERSn*¹ Error Passive Mode (TEC ≥ 128 or REC ≥ 128) IRR5
Not possible
Bus Off (TEC ≥ 256)/Bus Off recovery
IRR6
Error warning (TEC ≥ 96)
IRR3
Error warning (REC ≥ 96)
IRR4
OVRn*¹ Reset/halt/CAN sleep transition
IRR0
Overload frame transmission
IRR7
Unread message overwrite (overrun)
IRR9
Start of new system matrix
IRR10
TCMR2 compare match
IRR11
Bus activity while in sleep mode
IRR12
Timer overrun/Next_is_Gap reception/message IRR13
error
TCMR0 compare match
IRR14
TCMR1 compare match
IRR15
RMn0*¹*², Data frame reception
RMn1*¹*² _{Remote frame reception}
IRR1*³
IRR2*³
Possible*⁴
SLEn*¹ Message transmission/transmission disabled IRR8
(slot empty)
Not possible
Notes: 1. n = 0, 1
2. RM0 is an interrupt generated by the remote request pending flag for mailbox 0
(RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1 is an interrupt
generated by the remote request pending flag for mailbox n (RFPR0[n]) or the data
frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 31).
3. IRR1 is a data frame received interrupt flag for mailboxes 0 to 31, and IRR2 is a remote
frame request interrupt flag for mailboxes 0 to 31.
4. The DMAC is activated only by an RMn0 interrupt.
Rev. 2.00 Mar. 14, 2008 Page 1005 of 1824
REJ09B0290-0200