SH7263 Datasheet, PDF (1366/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
(b) Buffer Clearing
Table 25.17 shows the clearing of the buffer memory by this module. The buffer memory can be
cleared using the four bits indicated below.
Table 25.17 List of Buffer Clearing Methods
Bit Name
Register
Function
Clearing
method
BCLR
SCLR
DCLRM
CFIFOCTR
CFIFOSIE
DnFIFOSEL
DnFIFOCTR
Clears the buffer Clears the buffer
memory on the CPU memory on the SIE
side
side
In this mode, after
the data of the
specified pipe has
been read, the
buffer memory is
cleared
automatically.
Cleared by writing 1 Cleared by writing 1 1: Mode valid
0: Mode invalid
ACLRM
PIPEnCTR
This is the auto
buffer clear mode, in
which all of the
received packets
are destroyed.
1: Mode valid
0: Mode invalid
(c) Buffer Areas
Table 25.18 shows the FIFO buffer memory map of this controller. The buffer memory has special
fixed areas to which pipes are assigned in advance, and user areas that can be set by the user.
The buffer for the DCP is a special fixed area that is used both for control read transfers and
control write transfers.
The PIPE6 and PIPE7 area is assigned in advance, but the area for pipes that are not being used
can be assigned to PIPE1 to PIPE5 as a user area.
The settings should ensure that the various pipes do not overlap. Note that each area is twice as
large as the setting value in the double buffer.
Also, the buffer size should not be specified using a value that is less than the maximum packet
size.
Rev. 2.00 Mar. 14, 2008 Page 1332 of 1824
REJ09B0290-0200