SH7263 Datasheet, PDF (987/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
(1) Transmit Pending Register (TXPR1, TXPR0)
The concatenation of TXPR1 and TXPR0 is a 32-bit register that contains any transmit pending
flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as
two consecutive word accesses.
<Longword Write Operation>
<upper word write>
16-bit Peripheral bus
<lower word write>
16-bit Peripheral bus
Temp
consecutive access
Temp
TXPR1
H'020
TXPR0
H'022
Data is stored into Temp instead of TXPR1.
<Longword Read Operation>
<upper word read>
16-bit Peripheral bus
TXPR1
H'020
TXPR0
H'022
Longword data are stored into
both TXPR1 and TXPR0 at the same time.
<lower word read>
16-bit Peripheral bus
Temp
consecutive access
Temp
TXPR1
H'020
TXPR0
H'022
TXPR1
H'020
TXPR0
H'022
TXPR0 is stored into Temp,
when TXPR1 is read.
Temp is read instead of TXPR0.
The TXPR1 controls Mailbox-31 to Mailbox-16, and the TXPR0 controls Mailbox-15 to Mailbox-
1. The CPU may set the TXPR bits to affect any message being considered for transmission by
writing a ‘1’ to the corresponding bit location. Writing a ‘0’ has no effect, and TXPR cannot be
cleared by writing a ‘0’ and must be cleared by setting the corresponding TXCR bits. TXPR may
be read by the CPU to determine which, if any, transmissions are pending or in progress. In effect
there is a transmit pending bit for all Mailboxes except for the Mailbox-0. Writing a ‘1’ to a bit
location when the mailbox is not configured to transmit is not allowed.
Rev. 2.00 Mar. 14, 2008 Page 953 of 1824
REJ09B0290-0200