SH7263 Datasheet, PDF (1846/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
35.4.3 Bus Timing
Figure 35.21 Burst
ROM Read Cycle (One
Software Wait Cycle,
One Asynchronous
External Burst Wait
Cycle, Two Burst)
35.4.5 DMAC Timing
Table 35.10 DMAC
Timing
35.4.9 SSU Timing
Figure 35.55 SSU
Timing (Slave, CPHS =
1)
Page
1712
1737
1743
Figure 35.56 SSU
Timing (Slave, CPHS =
0)
35.4.11 SSI Timing
1746
Table 35.16 SSI Timing
A. Pin States
Table A.1 Pin States
1771
1776
Revision (See Manual for Details)
Figure amended
CSn
t_CSD1 t_AS
t_CS
t_CSD1
Table amended
Item
DACK, TEND delay time
Figure amended
Symbol Min.
t
0
DACD
Max. Unit
13
ns
Figure
Figure 35.47
SSI (output)
t_SA
t_OH
t_OD
Figure amended
SSI (output)
t_OH
t_OD
t_SA
Table amended
Item
Output clock cycle
Input clock cycle
Table amended
Symbol
tO
tI
Min.
80
80
Max.
64000
64000
Unit Remarks
ns Output
ns Input
Figure
Figure
35.58
Type
Clock
Pin Function
Pin State
Pin Name
Normal
Reset State Power-Down State
State (Other Power-
Deep Software Bus
than States On
Pin State Standby Standby Mastership
at Right)
Reset*¹ Retained*² Mode*³ Mode Release
CKIO
Clock 0, 1, 3 O/Z*⁶
operation
2
I
mode
O
O/Z*⁶*¹³
O/Z*⁶ O/Z*⁶
O/Z*⁶
I
I
Z
I
I
Note 4. amended
4. When pins for the connection with a crystal resonator are
not used, the input pins (EXTAL, RTC_X1, AUDIO_X1,
and USB_X1) must be fixed (pulled up, pulled down,
connected to power supply, or connected to ground) and
the output pins (XTAL, RTC_X2, AUDIO_X2, and
USB_X2) must be open.
Rev. 2.00 Mar. 14, 2008 Page 1812 of 1824
REJ09B0290-0200