SH7263 Datasheet, PDF (1614/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
(2) Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or power-
on reset). In clock modes 0, 1 and 3, clock signal starts to be output from the CKIO pin.
• Canceling by an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits
(IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC))
is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation
settling counter (WDT) used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR) of the WDT before the transition to software standby mode,
the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the
clock pulse will be supplied to the entire chip after this overflow. Software standby mode is
thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in case
of IRRQ) is started.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the
CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation
settling time.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters
software standby mode (when the clock pulse stops) and should be low when software standby
mode is canceled (when the clock is initiated after oscillation settling). When software standby
mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU
enters software standby mode (when the clock pulse stops) and should be high when software
standby mode is canceled (when the clock is initiated after oscillation settling). (The same
applies to the IRQ pin.)
• Canceling by a reset
When the RES pin is driven low, software standby mode is canceled and the LSI enters the
power-on reset state. After that, if the RES pin is driven high, the power-on reset exception
handling is started.
When the MRES pin is driven low, software standby mode is canceled and the LSI enters the
manual reset state. After that, if the MRES pin is driven high, the manual reset exception
handling is started.
Keep the RES or MRES pin low until the clock oscillation settles. The internal clock will
continue to be output to the CKIO pin in clock modes 0, 1 and 3.
Rev. 2.00 Mar. 14, 2008 Page 1580 of 1824
REJ09B0290-0200