SH7263 Datasheet, PDF (1483/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
(2) When Interrupts are Used to Activate DMAC
1. Assign IDEI of the SRC to one channel of the DMAC.
2. Set the IEN bit in SRCIDCTRL to 1.
3. When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued thus activating
the DMAC. When the DMAC has written data to the SRCID thus resulting in the number of
data units in the input data FIFO exceeding that of the triggering number specified by the
IFTRG1 and IFTRG 0 bits in SRCIDCTRL, the IINT bit is cleared to 0.
4. Repeat step 3 until all the data has been input, and write 1 to the FL bit in SRCCTRL.
27.3.3 Data Output
Figure 27.4 is a sample flowchart for data output.
Start data output
Read the OINT bit in SRCSTAT.
OINT = 1?
No
Yes
Read the data after conversion from
SRCOD and clear the OINT bit to 0.
Flash processing
No
started?
Yes
Read the FLF bit in SRCSTAT.
No
FLF = 0?
Yes
Data output completed
Figure 27.4 Sample Flowchart for Data Output
Rev. 2.00 Mar. 14, 2008 Page 1449 of 1824
REJ09B0290-0200