SH7263 Datasheet, PDF (697/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Peripheral clock
(Pφ)
Counter clock
Clock
N+1
Section 12 Compare Match Timer (CMT)
CMCNT
N
0
CMCOR
N
Compare match
signal
Figure 12.4 Timing of CMF Setting
12.4.3 Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of
the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by
the DMAC.
Rev. 2.00 Mar. 14, 2008 Page 663 of 1824
REJ09B0290-0200