SH7263 Datasheet, PDF (1084/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
Initial
Bit
Bit Name Value R/W Description
6
TXS
0
R/(W)* Transmit Start
Indicates that the IEB starts transmission.
[Setting conditions]
• During master transmission, the arbitration is won
and the master address field transmission is
completed
[Clearing condition]
• When 1 is written
5
TXF
0
R/(W)* Transmit Normal Completion
Indicates that data for the number of bytes specified by
the message length bits has been transmitted with no
error.
[Setting condition]
• When data for the number of bytes specified by the
message length bits has been transmitted normally
[Clearing condition]
• When 1 is written
4
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
TXEAL
0
R/(W)* Arbitration Loss
The IEB retransmits from the start bit for the number of
times specified by the RN bit in IEMCR if the arbitration
has been lost in master communications. If the
arbitration has been lost for the specified number of
times, the TXEAL is set to enter the wait state. If the
arbitration has been won within retransmit for the
specified number of times, this flag is not set to 1. This
flag is set only when the arbitration has been lost and
the wait state is entered.
[Setting condition]
• When the arbitration has been lost during data
transmission and the transmission has been
terminated
[Clearing condition]
• When 1 is written
Rev. 2.00 Mar. 14, 2008 Page 1050 of 1824
REJ09B0290-0200