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| SH7263 Datasheet, PDF (370/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 9 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*1
CS3
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Tr
Tc1
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.25 Single Write Timing (Bank Active, Different Bank)
Rev. 2.00 Mar. 14, 2008 Page 336 of 1824
REJ09B0290-0200
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