SH7263 Datasheet, PDF (1009/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
(6) Timer Counter Register (TCNTR)
This is a 16-bit read/write register that allows the CPU to monitor and modify the value of the
Free Running Timer Counter. When the Timer meets TCMR0 (Timer Compare Match Register 0)
+ TTCR0 [6] is set to ‘1’, the TCNTR is cleared to H'0000 and starts running again. In Time-
Trigger mode, this timer can be used as Local Time and TTCR0[6] has to be cleared to work as a
free running timer.
Notes: 1. It is possible to write into this register only when it is enabled by the bit 15 in TTCR0.
If TTCR0 bit15 = 0, TCNTR is always H'0000.
2. There could be a delay of a few clock cycles between the enabling of the timer and the
moment where TCNTR starts incrementing. This is caused by the internal logic used
for the pre-scaler.
• TCNTR (Address = H'08C)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCNTR[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * The register can be written only when enabled in TTCR0[15]. Write operation is not
allowed in Time Trigger mode (i.e. CMAX is not 3'b111).
Bit 15 to 0 — Indicate the value of the Free Running Timer.
(7) Cycle Time register (CYCTR)
This register is a 16-bit read-only register. This register shows Cycle Time = Local Time
(TCNTR) - Reference_Mark (RFMK). In ET mode this register is the exact copy of TCNTR as
RFMK is always fixed to zero.
• CYCTR (Address = H'090)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CYCTR[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 2.00 Mar. 14, 2008 Page 975 of 1824
REJ09B0290-0200