SH7263 Datasheet, PDF (1345/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Access Transfer
Direction Direction Pipe
Conditions under which BRDY Interrupts are
BFRE DBLB Generated
Write
Transmit 1 to 7 0
1
(1), (2), (3), (4) or (5) below:
(1) Software changes the direction of transfer
direction from receiving to transmitting.
(2) Data is enabled to be transmitted by one of
(a) to (c) below, when there is no data
waiting to be transmitted in buffer:
(a) Buffer becomes full by writing data n
times the maximum packet size (n = 1
during a non-continuous transfer).
(b) Software sets the BVAL bit in
DnFIFOCTR to 1 to enable the buffer to
transmit data.
(c) Writing is completed in DMA transfer.
(3) Transmission of data from one buffer is
complete when there are data waiting to be
transmitted in both buffers
(4) Software sets the ACLRM bit to 1 when
there are data waiting to be transmitted in
both buffers.
(5) Software sets the SCLR bit to 1 when there
are data waiting to be transmitted in both
buffers.
1
Don't Not generated
care
Note: In non-continuous transfer (CNTMD = 0), “buffer full” means that the maximum packet size
of data has been received. In continuous transfer (CNTMD = 1), it means that the buffer
size of data has been received.
If a zero-length packet has been received, the corresponding bit in BRDYSTS is set to 1 but data
in the corresponding packet cannot be read. The buffer should be cleared (BCLR = 1) after
clearing BRDYSTS.
With PIPE1 to PIPE7, if DMA transfer is performed in the reading direction, interrupts can be
generated in transfer units, by setting the BFRE bit in PIPECFG to 1.
Rev. 2.00 Mar. 14, 2008 Page 1311 of 1824
REJ09B0290-0200