SH7263 Datasheet, PDF (1486/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
27.5 Usage Note
27.5.1 Note on Register Access
After a 1 has been written to the FL bit in SRCCTRL, three cycles of the peripheral clock (Pφ)
elapse before setting of the FLF bit in SRCSTAT. On the other hand, as the CPU executes any
subsequent instruction without waiting for the completion of the register writing, an instruction
that immediately follows that used to write to SRCCTRL cannot accurately detect the state of FLF
being set. To check the state of execution of flush processing, wait for the FLF bit to be set by
dummy-reading SRCCTRL or SRCSTAT after the instruction used to write to SRCCTRL.
27.5.2 Note on Flush Processing
When 1 is written to the FL bit in the SRC control (SRCCTRL) register, the SRC continues
conversion processing, appending zeros after the endpoint of the data input up to that point.
Perform flush processing when input of audio data up to the endpoint has completed and there is
no following data.
To restart conversion processing after flush processing, use one of the following methods to clear
the work memory.
• Write 1 to the CL bit in SRCCTRL.
• Write 0 followed by 1 to the SRCEN bit in SRCCTRL.
Rev. 2.00 Mar. 14, 2008 Page 1452 of 1824
REJ09B0290-0200