SH7263 Datasheet, PDF (1387/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.25 Error Detection when a Data Packet is Received
Detection
Priority Order
1
2
3
Error
PID errors
CRC error and bit stuffing errors
Maximum packet size exceeded error
Generated Interrupt and Status
No interrupts are generated (ignored as
a corrupted packet)
An NRDY interrupt is generated to set
the CRCE bit in both cases when the
host controller function is selected and
the function controller function is
selected.
A BEMP interrupt is generated to set
the PID bits to STALL in both cases
when the host controller function is
selected and the function controller
function is selected.
(2) DATA-PID
Because High Bandwidth transfers are not supported, the DATA-PID added with the USB 2.0
standard is supported as shown below.
1. IN direction
⎯ DATA0: Sent as data packet PID
⎯ DATA1: Not sent
⎯ DATA2: Not sent
⎯ mDATA: Not sent
2. OUT direction (when using full-speed operation)
⎯ DATA0: Received normally as data packet PID
⎯ DATA1: Received normally as data packet PID
⎯ DATA2: Packets are ignored
⎯ mDATA: Packets are ignored
3. OUT direction (when using high-speed operation)
⎯ DATA0: Received normally as data packet PID
⎯ DATA1: Received normally as data packet PID
⎯ DATA2: Received normally as data packet PID
⎯ mDATA: Received normally as data packet PID
Rev. 2.00 Mar. 14, 2008 Page 1353 of 1824
REJ09B0290-0200