SH7263 Datasheet, PDF (1434/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus clock interval when the LCDC reads VRAM. As the LCDC does not
access VRAM during the bus clock period specified by LDLIRNR, external bus accesses by the
CPU or the DMAC is possible during that period.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- LIRN7 LIRN6 LIRN5 LIRN4 LIRN3 LIRN2 LIRN1 LIRN0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 8
Bit Name
⎯
7 to 0
LIRN7 to
LIRN0
Initial
Value R/W
All 0 R
All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
VRAM Read Bus Clock Interval
These bits specify the number of the bus clocks that are
inserted during burst bus cycles to read VRAM by the
LCDC.
H'00: One bus clock
H'01: Two bus clocks
:
H'FF: 256 bus clocks
CKIO
Bus cycle LCDC1 LCDC2 LCDC3 ^... LCDC16
CPU
CPU
...
CPU
LCDC1
...
16 bursts
(When displaying routated image,
4/8/16/32 can be selected.)
The number of bus clocks other than LCDC is set to
LIRN7 to LIRN0. (1 to 256 bus clocks)
Rev. 2.00 Mar. 14, 2008 Page 1400 of 1824
REJ09B0290-0200