SH7263 Datasheet, PDF (453/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
Transfer
DMA Transfer Request Signal Source
Transfer Bus
Destination Mode
1000 001000 11 SSI_0
DMA0 (transmission mode)
DMA0 (reception mode)
Any
SSIRDR0
SSITDR0
Any
Cycle
steal
001001 11 SSI_1
DMA1 (transmission mode)
Any
SSITDR1
DMA1 (reception mode)
SSIRDR1 Any
001010 11 SSI_2
DMA2 (transmission mode)
Any
SSITDR2
DMA2 (reception mode)
SSIRDR2 Any
001011 11 SSI_3
DMA3 (transmission mode)
Any
SSITDR3
DMA3 (reception mode)
SSIRDR3 Any
010000 01 SRC input
IDEI (input data FIFO empty) Any
SRCIDR
10 SRC output
ODFI (output data FIFO full)
SRCODR Any
010100 01 SSU_0
transmission
SSTXI0 (transmission empty or Any
transmission end)
SSTDR0 to Cycle
SSTDR3 steal
10 SSU_0
reception
SSTXI0 (reception full)
SSRDR0 to Any
SSRDR3
010101 01 SSU_1
transmission
SSTXI1 (transmission empty or Any
transmission end)
SSTDR0 to
SSTDR3
10 SSU_1
reception
SSTXI1 (reception full)
SSRDR0 to Any
SSRDR3
011000 01 IIC3_0
transmission
TXI0 (transmission data empty) Any
ICDRT0
10 IIC3_0
reception
RXI0 (reception data full)
ICDRR0 Any
011001 01 IIC3_1
transmission
TXI1 (transmission data empty) Any
ICDRT1
10 IIC3_1
reception
RXI1 (reception data full)
ICDRR1 Any
011010 01 IIC3_2
transmission
TXI2 (transmission data empty) Any
ICDRT2
10 IIC3_2
reception
RXI2 (reception data full)
ICDRR2 Any
Rev. 2.00 Mar. 14, 2008 Page 419 of 1824
REJ09B0290-0200