SH7263 Datasheet, PDF(1096/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (1096/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 20 IEBusTM Controller (IEB)

20.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128)

IETB001 to IETB128 are 128-byte (8 Ã 128) buffers to which data to be transmitted during master

transmission is written.

The initial values in IETB001 to IETB128 are undefined.

Bit: 7

6

5

4

3

2

1

0

TBn

Initial value: -

-

-

-

-

-

-

-

R/W: W* W* W* W* W* W* W* W*

[Legend]

n = 001 to 128

Initial

Bit

Bit Name Value

R/W Description

7 to 0 TBn

Undefined W* IEBus Transmit Data Buffer

Data to be transmitted in the data field during master

transmission is written to TB001 to TB128.

Data is written starting with TB001 for the start 1-byte

data, followed by TB002 and TB003 and so on

according to the transmission order, and TB128 stores

the last data.

Note: * Writing to these bits during master transmission (MRQ in IEFLG is 1) is prohibited

Rev. 2.00 Mar. 14, 2008 Page 1062 of 1824

REJ09B0290-0200

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