SH7263 Datasheet, PDF (1140/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.15 Decoding Stoppage Source Status Register (CBUFST1)
The decoding stoppage source status register (CBUFST1) indicates that decoding/buffering has
been stopped due to some errors.
A bit in this register can only be set when the corresponding bit in the CROMCTL3 register is set
to 1.
Bit: 7
6
5
4
3
2
1
0
BUF_ BUF_
ECC EDC
-
BUF_ BUF_
MD MIN
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Initial
Bit Bit Name Value
7
BUF_ECC 0
6
BUF_EDC 0
5
⎯
0
4
BUF_MD 0
3
BUF_MIN 0
2 to 0 ⎯
All 0
R/W Description
R
Indicates that decoding and buffering have been
stopped because of an error that is not correctable by
using the ECC.
R
Indicates that decoding and buffering have been
stopped because the post-correction EDC check
indicated an error.
R
Reserved
This bit is always read as 0 and cannot be modified.
R
Indicates that decoding and buffering have been
stopped because the current sector is in a mode or form
differing from that of the previous sectors.
R
Indicates that decoding and buffering have been
stopped because a non-sequential minutes, seconds, or
frames (1/75 second) value has been encountered.
R
Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 2.00 Mar. 14, 2008 Page 1106 of 1824
REJ09B0290-0200