SH7263 Datasheet, PDF (1295/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Bit
Bit Name
11 to 6 ⎯
5
SIGNE
4
SACKE
3
⎯
2
BRDYM
1, 0
⎯
Section 25 USB 2.0 Host/Function Module (USB)
Initial
Value
All 0
0
0
0
0
All 0
R/W
R
R/W
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Setup Transaction Error Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled
Setup Transaction Normal Response Interrupt
Enable
0: Interrupt output disabled
1: Interrupt output enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
BRDY Interrupt Status Clear Timing Control for Each
Pipe
0: Software clears the status.
1: This module clears the status by reading from or
writing to the FIFO buffer.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1261 of 1824
REJ09B0290-0200