SH7263 Datasheet, PDF (1180/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.5.2 Timing of Status Registers Updates
The status information registers of the CD-ROM decoder are updated on each ISEC interrupt. The
sector for which information is reflected in the status registers is selected by the ER0SEL bit of the
CROMCTL4 register.
Rev. 2.00 Mar. 14, 2008 Page 1146 of 1824
REJ09B0290-0200