English
Language : 

SH7263 Datasheet, PDF (1613/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Section 32 Power-Down Modes
32.3.2 Software Standby Mode
(1) Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit and DEEP bit in STBCR are 1 and 0 respectively. In
software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
The clock output from the CKIO pin also stops in clock modes 0, 1 and 3.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. As for the states of on-chip peripheral module
registers in software standby mode, see section 34.3, Register States in Each Operating Mode.
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
values to secure the specified oscillation settling time.
3. After setting the STBY and DEEP bits in STBCR to 1 and 0 respectively, read STBCR. Then,
execute a SLEEP instruction.
Rev. 2.00 Mar. 14, 2008 Page 1579 of 1824
REJ09B0290-0200