SH7263 Datasheet, PDF (1776/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.10 IIC3 Timing
Table 35.15 IIC3 Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Symbol Min.
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
t_SCL
t_SCLH
t_SCLL
12
t *1
pcyc
+
600
3
t *1
pcyc
+
300
5
t *1
pcyc
+
300
SCL, SDA input rise time
t_Sr
—
SCL, SDA input fall time
t_Sf
—
SCL, SDA input spike pulse removal time*² t_SP
—
SDA input bus free time
t_BUF
5
Start condition input hold time
t_STAH
3
Retransmit start condition input setup time t_STAS
3
Stop condition input setup time
Data input setup time
t_STOS
t_SDAS
3
1
t *1
pcyc
+
20
Data input hold time
t_SDAH
0
SCL, SDA capacitive load
Cb
0
SCL, SDA output fall time*³
t_Sf
—
Notes: 1. t_pcyc indicates the peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
Max.
—
—
—
300
300
1, 2
—
—
—
—
—
—
400
250
Unit Figure
ns Figure 35.57
ns
ns
ns
ns
t *¹
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Rev. 2.00 Mar. 14, 2008 Page 1742 of 1824
REJ09B0290-0200