SH7263 Datasheet, PDF (434/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Bit
13, 12
Bit Name
SM[1:0]
11 to 8 RS[3:0]
Initial
Value R/W Description
00
0000
R/W Source Address Mode
These bits select whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with
DACK.)
00: Fixed source address
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte-unit transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer, setting prohibited in 16-byte-unit
transfer)
11: Setting prohibited
R/W Resource Select
These bits specify which transfer requests will be sent
to the DMAC. The changing of transfer request source
should be done in the state when DMA enable bit (DE)
is set to 0.
0000: External request, dual address mode
0001: Setting prohibited
0010: External request/single address mode
External address space → External device with
DACK
0011: External request/single address mode
External device with DACK → External address
space
0100: Auto request
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1000: DMA extension resource selector
1001: RCAN-TL10
1010: RCAN-TL11
1011: Setting prohibited
1100: Setting prohibited
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Note: External request specification is valid only in
CHCR_0 to CHCR_3. If a request source is
selected in channels CHCR_4 to CHCR_7, no
operation will be performed.
Rev. 2.00 Mar. 14, 2008 Page 400 of 1824
REJ09B0290-0200