SH7263 Datasheet, PDF (1229/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Bit
26
25
24
23, 22
21
20
Initial
Bit Name Value
ADRMD 0
CDSRC 0
DOSR
0
—
All 0
SELRW 0
DOADR 0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Sector Access Address Specification
This bit is invalid in command access mode. This bit is
valid only in sector access mode.
0: The value of the address register is handled as a
physical sector number. Use this value usually in
sector access.
1: The value of the address register is output as the
address of flash memory.
Note: Clear this bit to 0 in continuous sector access.
Data Buffer Specification
Specifies the data buffer to be read from or written to in
the data stage in command access mode.
0: Specifies FLDATAR as the data buffer.
1: Specifies FLDTFIFO as the data buffer.
Status Read Check
Specifies whether or not the status read is performed
after the second command has been issued in
command access mode.
0: Performs no status read
1: Performs status read
Reserved
These bits are always read as 0. The write value should
always be 0.
Data Read/Write Specification
Specifies the direction of read or write in data stage.
0: Read
1: Write
Address Stage Execution Specification
Specifies whether or not the address stage is executed
in command access mode.
0: Performs no address stage
1: Performs address stage
Rev. 2.00 Mar. 14, 2008 Page 1195 of 1824
REJ09B0290-0200