SH7263 Datasheet, PDF (1378/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Writing of the CURPIPE bit
PMS_N
CURPIPE PIPE-A
FRDY
DTLN
PIPE-A
PIPE-A
PIPE-B
Undefined
Undefined
PIPE-B
PIPE-B
max. 50 ns +
bus clock × 3
min. 20 ns
max. 450 ns +
bus clock × 8
Figure 25.15 Timing at which the FRDY and DTLN Bits are Determined after
Changing a Pipe
(b) Timing at which the FIFO Port can be Accessed after Reading/Writing has been
Completed when Using a Double Buffer
Figure 25.16 shows the timing at which, when using a pipe with a double buffer, the other buffer
can be accessed after reading from or writing to one buffer has been completed.
When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns and
6 clock cycles at a peripheral clock after the access made just prior to toggling.
The same timing applies when a short packet is being sent based on the BVAL = 1 setting using
the IN direction pipe.
Access just prior to buffer toggling
PMS_N
CURPIPE
FRDY
DTLN
Buffer-A
Buffer-A
PIPE-A
Undefined
Buffer-B
Buffer-B
min. bus clock × 1
max. 300 ns +
bus clock × 6
Figure 25.16 Timing at which the FRDY and DTLN Bits are Determined after Reading
from or Writing to a Double Buffer has been Completed
Rev. 2.00 Mar. 14, 2008 Page 1344 of 1824
REJ09B0290-0200