SH7263 Datasheet, PDF (26/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

22.3 Register Descriptions....................................................................................................... 1154
22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................ 1155
22.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1156
22.4 Operation ......................................................................................................................... 1160
22.4.1 Single Mode........................................................................................................ 1160
22.4.2 Multi Mode ......................................................................................................... 1163
22.4.3 Scan Mode .......................................................................................................... 1165
22.4.4 A/D Converter Activation by External Trigger or MTU2 .................................. 1168
22.4.5 Input Sampling and A/D Conversion Time ........................................................ 1168
22.4.6 External Trigger Input Timing............................................................................ 1170
22.5 Interrupt Sources and DMAC Transfer Request .............................................................. 1171
22.6 Definitions of A/D Conversion Accuracy........................................................................ 1172
22.7 Usage Notes ..................................................................................................................... 1173
22.7.1 Module Standby Mode Setting ........................................................................... 1173
22.7.2 Setting Analog Input Voltage ............................................................................. 1173
22.7.3 Notes on Board Design ....................................................................................... 1173
22.7.4 Processing of Analog Input Pins......................................................................... 1174
22.7.5 Permissible Signal Source Impedance ................................................................ 1175
22.7.6 Influences on Absolute Precision........................................................................ 1176
22.7.7 A/D Conversion in Deep Standby Mode ............................................................ 1176
22.7.8 Note on Usage in Scan Mode and Multi Mode................................................... 1176
Section 23 D/A Converter (DAC) ................................................................... 1177
23.1 Features............................................................................................................................ 1177
23.2 Input/Output Pins............................................................................................................. 1178
23.3 Register Descriptions....................................................................................................... 1179
23.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)........................................... 1179
23.3.2 D/A Control Register (DACR) ........................................................................... 1180
23.4 Operation ......................................................................................................................... 1182
23.5 Usage Notes ..................................................................................................................... 1183
23.5.1 Module Standby Mode Setting ........................................................................... 1183
23.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1183
23.5.3 Setting Analog Input Voltage ............................................................................. 1183
23.5.4 D/A Conversion in Deep Standby Mode ............................................................ 1183
Section 24 AND/NAND Flash Memory Controller (FLCTL) ........................ 1185
24.1 Features............................................................................................................................ 1185
24.2 Input/Output Pins............................................................................................................. 1189
24.3 Register Descriptions....................................................................................................... 1190
24.3.1 Common Control Register (FLCMNCR) ........................................................... 1191
Rev. 2.00 Mar. 14, 2008 Page xxvi of xxxiv
REJ09B0290-0200